1. Field
Exemplary implementations of the present invention relate to a nonvolatile memory device, and more particularly, to a nonvolatile memory including memory cells stacked arranged in a three-dimensional manner.
2. Description of the Related Art
A demand for high integration of memory devices is increasing. Conventionally, an integration degree of a memory device has been increased by reducing the size of memory cells that are two-dimensionally arranged over a semiconductor substrate. However, there is a physical limit to reducing the size of memory cells. For this reason, a method for increasing the integration degree of a memory device by three-dimensionally arranging memory cells over a semiconductor substrate has been proposed, as disclosed in Korean Patent Laid-open Publication No. 2013-005434. When the memory cells are arranged in a three-dimensional manner, the area of the semiconductor substrate may be efficiently utilized, and the integration degree may be improved more than when the memory cells are arranged in a two-dimensional manner.
FIG. 1 is a configuration diagram of a conventional three-dimensional nonvolatile memory device.
Referring to FIG. 1, the three-dimensional nonvolatile memory device includes a plurality of memory blocks BLK1 to BLK3.
In an X-Y plane of FIG. 1, one memory block includes two cell strings. For example, the memory block BLK2 includes two cell strings formed in a U-shape. A first cell string of the memory block BLK2 includes memory cells stacked between a drain select transistor, controlled by a drain select line DSL0, and a pipe transistor, corresponding to a left transistor of transistors controlled by a pipe gate PG, and memory cells stacked between the pipe transistor, corresponding to the left transistor of transistors controlled by the pipe gate PG, and a source select transistor corresponding to a left transistor of transistors controlled by a source select line SSL. The memory cells stacked between the drain select transistor and the pipe transistor are controlled by word lines WL8 to WL15 and the memory cells stacked between the pipe transistor and the source select transistor are controlled by word lines WL0 to WL7. Furthermore, a second cell string of the memory block BLK2 includes memory cells stacked between a drain select transistor, controlled by a drain select line DSL1, and a pipe transistor, corresponding to a right transistor of transistors, controlled by the pipe gate PG and memory cells stacked between the pipe transistor, corresponding to the right transistor of transistors controlled by the pipe gate PG, and a source select transistor corresponding to a right transistor of transistors controlled by the source select line SSL. The memory cells stacked between the drain select transistor and the pipe transistor are controlled by the word lines WL8 to WL15, and the memory cells stacked between the pipe transistor and the source select transistor are controlled by the word lines WL0 to WL7.
Each of the memory blocks BLK1 to BLK3 corresponds to the unit of an erase operation among operations of the nonvolatile memory device. Furthermore, except for a bit line BL and a source line SL in FIG. 1, lines represented by the same symbols but belonging to different memory blocks are different from each other. For example, different voltages may be applied to the cord line WL of the memory block BLK1 and the word line WL3 of the memory block BLK2, respectively.
FIG. 2 is a cross-sectional view of FIG. 1. Referring to FIG. 2, it can be seen that cells strings are arranged in a Z-axis direction as well as on the X-Y plane of FIG. 1. In FIGS. 2, 201, 202, 203, and 204 represent insulators for isolating word lines WL of the respective memory blocks BLK1, BLK2, and BLK3. For example, the insulator 202 electrically isolates word lines WL<15:8> of the memory block BLK1 from word lines WL<15:8> of the memory block BLK2. Thus, the memory blocks BLK1 and BLK2 may independently operate.
Since two adjacent cell strings share the word lines WL<7:0>, among the word lines of the memory blocks BLK1 to BLK3, the word lines WL<7:0> may have a large width. However, since adjacent cell strings do not share the word lines WL<15:8>, the word lines WL<15:8> have a width smaller than the width of word lines WL<7:0>. Since the word lines WL<15:8> have a smaller width, they have a large resistance value. Thus, the word lines WL<15:8> may degrade the performance of the nonvolatile memory device. Furthermore, when the word lines WL 15:8>, having a smaller width, are stacked to fabricate the nonvolatile memory device, the difficulty level of the fabrication process inevitably increases.